Interface Solution

Updated On:2018-07-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Compensation > DDR3/3L - Compensation 
Cell Name Descriptions Type Process Gradation Literature
FXDDR3COMP100HH0L DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device Analog_IP 40nm Silver
FXDDR3COMPFC502HH0L DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process Analog_IP 40nm Contact Sales
 
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver
FXDDR3LTCOMP100HH0L compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process . Analog_IP 40nm Silver