Logic Libraries

Updated On:2018-07-17
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,

Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
Logic Libraries > IO Cell Library
> Analog ESD IO Library > True 3.3V Analog ESD IO Library 
Cell Name Descriptions Type Process Gradation Literature
UMC 40nm LP/RVT Logic Process, 3.3V Analog ESD IO cell Library (using 2.5V overdrive 3.3V MOS) Library_Group 40nm Silver