Analog

Updated On:2018-07-17
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> Digitized DLL > 500M ~ 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HH0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 40nm LP/RVT LowK Logic Process Analog_IP 40nm Silver Minus
FXADDLL330HH0L An ADDLL operate at 300MHz~600MHz. Output 0-180 degree Phase adjustment range. Delay adjustment resolution <= 1% of reference clock UMC 40nm LP/RVT Logic Process. Analog_IP 40nm Silver
FXADDLL350HH0L Input 360M-720M Hz, output 360M-720M Hz, DLL;Output 0-180 degree Phase adjustment range. UMC 40nm LP process. Analog_IP 40nm Bronze