Analog

Updated On:2018-07-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> DLL > 20M ~ 500M, DLL 
Cell Name Descriptions Type Process Gradation Literature
FXDLL340HH0L Input 80MHz-280MHz, DQS delay 3.125%-50% of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Silver Minus
FXDLL344HH0L Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process. Analog_IP 40nm Bronze