Logic Libraries

Updated On:2018-07-22
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Logic Libraries > ECO Core Cell Library
> 8-Track > 8T HVT ECO Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_DHS_ECO_M1_COR
E
UMC 55nm eFlash/HVT LowK Logic Process 8-track Standard Core Library Library_Group 55nm Silver
FSF0G_DHE_ECO_M1_COR
E
UMC 55nm uLP SST PROCESS HVT 8-track C60 standard cell ECO_M1 library Library_Group 55nm Bronze
FSF0L_DHS_ECO_M1_COR
E
UMC 55nm LP/HVT LowK Logic Process 8-Tracks ECO Core Cell Library Library_Group 55nm Silver
FSF0U_DHA_ECO_M1_COR
E
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90). W/O deep Nwell. Library_Group 55nm Silver
FSF0U_DHB_ECO_M1_COR
E
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) Library_Group 55nm Silver
FSF0U_DHS_ECO_M1_COR
E
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) w/ Forward Bias. W/ deep Nwell Library_Group 55nm Silver
FSF0U_DHU_ECO_M1_COR
E
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell Library_Group 55nm Silver
 
Logic Libraries > ECO Core Cell Library
> 8-Track > 8T LVT ECO Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0F_DLS_ECO_M1_COR
E
UMC 55nm eFlash/LVT LowK Logic Process 8-track Standard Core Library Library_Group 55nm Silver
FSF0L_DLS_ECO_M1_COR
E
UMC 55nm LP/LVT LowK Logic Process 8-Tracks ECO Core Cell Library Library_Group 55nm Silver
FSF0U_DLS_ECO_M1_COR
E
UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) Library_Group 55nm Silver
 
Logic Libraries > ECO Core Cell Library
> 8-Track > 8T RVT ECO Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0A_DRS_ECO_M1_COR
E
UMC 55nm SP/RVT LowK Logic Process miniLib Metal1 Start ECO core cell library Library_Group 55nm Bronze
FSF0F_DRS_ECO_M1_COR
E
UMC 55nm eFlash/RVT LowK Logic Process 8-track ECO_M1 cell Library Library_Group 55nm Silver
FSF0G_DRE_ECO_M1_COR
E
UMC 55nm uLP SST PROCESS RVT 8-track C60 standard cell ECO_M1 library Library_Group 55nm Bronze
FSF0L_DRS_ECO_M1_COR
E
UMC 55nm LP/RVT LowK Logic Process 8-Tracks ECO Core Cell Library Library_Group 55nm Silver
FSF0U_DRS_ECO_M1_COR
E
UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60) Library_Group 55nm Silver
 
Logic Libraries > ECO Core Cell Library
> 8-Track > 8T uHVT ECO Library 
Cell Name Descriptions Type Process Gradation Literature
FSF0G_DUU_ECO_M1_COR
E
UMC 55nm uLP SST PROCESS uHVT 8-track C90 standard cell ECO_M1 library Library_Group 55nm Bronze
FSF0U_DUU_ECO_M1_COR
E
UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell. Library_Group 55nm Silver