Interface Solution

Updated On:2018-07-16
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Interface Solution > DDR
> DDR PHY - Command/Address > DDR2 - Command/Address 
Cell Name Descriptions Type Process Gradation Literature
FXDDR2A173HF0A DDR2/MDDR Combo PHY CMD ADDR block ; UMC 55nm SP/RVT Lowk Process with 2.5V device Analog_IP 55nm Silver
FXDDR2A174HF0A DDR2/MDDR PHY CMD/ADDR BLOCK for DIMM usage; UMC 55nm 1.0V with 2.5V device SP/RVT LowK Logic Process Analog_IP 55nm Silver