Analog

Updated On:2018-07-17
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> PLL > 20M ~ 500M, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPLL004HF0L Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process. Analog_IP 55nm Silver Minus
FXPLL010HF0A Input 10M-310M Hz, output 20M-310M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Process Analog_IP 55nm Contact Sales
 
FXPLL010HF0L Input 10M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process Analog_IP 55nm Silver
FXPLL060HF0A Input 20M-200M Hz, output 20M-300M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT Low-K Logic Process Analog_IP 55nm Silver
FXPLL327HF0L Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process Analog_IP 55nm Silver
FXPLL362HF0L Input 200MHz - 400MHz, output clock_1X 200MHz - 400MHz, output clock_2X 400MHz - 800MHz, output clock_4X 800MHz-1600MHz,frequency synthesizable PLL;UMC 55nm LP/RVT LowK Logic process Analog_IP 55nm Silver Minus
FXPLLG011HF0L Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process Analog_IP 55nm Contact Sales