Analog

Updated On:2018-07-18
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> PLL > 500M ~ 1G, Generic PLL 
Cell Name Descriptions Type Process Gradation Literature
FXPCPLL050HF0A_APGD Input 40k-110kHz, output 72M-594MHz, frequency synthesizable PLL; UMC 55 nm Logic SP/RVT Low-K Process Analog_IP 55nm Bronze
 
FXPLL032HF0A Input 10M-200M Hz, output 300M-600M Hz, frequency synthesizable PLL ; UMC 55nm SP Low-K Logic Process Analog_IP 55nm Silver
FXPLL033HF0A Input 20M-50M Hz, output 300M-600M Hz, frequency synthesizable PLL; UMC 55nm SP/RVT process Analog_IP 55nm Silver Minus
FXPLL350HF0A Input 33.33M-100M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm SP-RVT Low-K process Analog_IP 55nm Silver
FXPLL360HF0F Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXPLL360HF0G Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process Analog_IP 55nm Silver Minus
FXPLL360HF0L Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver
FXPLL610HF0F Input 2MHz~16MHz, output 16~1000MHz, 1.08~1.32V small-size PLL; UMC 55nm Eflash Process. Analog_IP 55nm Bronze