Analog

Updated On:2018-07-20
Gradation
Faraday IPs are rated according to the IPs’ maturity and customer acceptance. They are graded by the rules described as below,


Platinum P Five (5) productions verified
Gold G Mass production proven
Silver S Silicon proven, Formal release
Silver Minus S- Manufacturing onging
Bronze B Pre-Silicon release
 
Analog > Clock
> Digitized DLL > 500M ~ 1G, Digitalized DLL 
Cell Name Descriptions Type Process Gradation Literature
FXADDLL310HF0A Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 55nm SP/RVT LowK Logic Process Analog_IP 55nm Bronze
FXADDLL310HF0L Input 333M-800MHz, output 333M-800MHz, all digital DLL with one-channel DQS delay range ; UMC 55nm LP/RVT LowK Logic Process Analog_IP 55nm Silver Minus
 
FXADDLL340HF0A Input 333M-800MHz, output 333M-800MHz, all digital DLL with per 1/64UI programmable delay ; UMC 55nm SP/RVT Low-K Logic Process Analog_IP 55nm Silver