| Job Positions |
Descriptions |
Location |
| RTL Designer (Entry Level) |
- Masters/Bachelors in Electrical/Electronics/Computer Engineering or any related field.
- Ideal candidate may have 0 to 3 yrs of experience.
- Will be working as RTL design & verification engineer in DDR/LPDDR PHY IP development team.
- Perform RTL coding, CDC/RDC and Lint checks.
- Develop and maintain testbench for block level verification.
- Understand functionality of designs and develop testcases.
Skill requirements:
- Good knowledge of digital design concepts.
- Good knowledge of Verilog and RTL design fundamentals.
- Good knowledge of system verilog and UVM.
- Strong debugging skills.
- Familiar with EDA tools used for RTL design/verification, Lint, CDC/RDC, Synthesis.
- Ability to co-work with team-members and should be a good team-player.
- Good communication and presentation skills.
|
Bengaluru, India |
| Analog Layout Designer |
- Responsible for Layout Design and development of analog, mixed-signal, IOs and custom digital blocks.
- Should understand design constraints and responsible for on-time delivery of quality layouts.
- Ownership in area estimation, scheduling and execution to meet project deadlines.
- Perform physical layout verification, quality checks and support documentation.
- Expertise in Synopsys custom compiler, Virtuoso XL, DRC/LVS/Extraction(Mentor Graphics/Synopsys).
- Knowledge in scripting languages (Skill, Perl, TCL, SVRF etc ).
- Understanding layout effects such as speed, capacitance, power, area, etc.
- Decent understanding of analog Layout fundamentals like Matching, Electro-migration, Latch-up, coupling, IR-drop etc.).
- Follow good layout practices which help in easy porting and maintenance.
- Ability to work closely with team-members and should be a good team player.
- Positive approach for debugging and problem solving.
- 5-year experience is needed
|
Bengaluru, India |
| Analog circuit designer (senior-level) |
- Analog circuit design Engineer for DDR PHY IP development team.
- Masters/Bachelors in Electrical/Electronics Engineering or any related field.
- The role would include circuit design and support of analog blocks of DDR PHY solution of Faraday. All leading DDR protocols are supported – such as DDR3/DDR4/DDR5/LPDDR4/LPDDR4x/LPDDR5/LPDDR5x.
The work involved:
- Working with layout and digital teams to design analog blocks for an optimized DDR/LPDDR PHY.
- Should take responsibility for all analog PHY blocks.
- Guiding junior analog circuit designers.
- Close interaction with layout team for effective layouts in-terms of performance.
- Working with digital designers to come up with DRAM and PHY training algorithms for effective system performance.
- Working on post-silicon validation.
Skill requirements:
- More than 8yr exp in analog circuit design.
- Prior experience in the design of Tx and Rx of High-speed IOs is a must. Experience in DDR/LPDDR I/Os will be a plus.
- Good exposure to the design of critical analog blocks like bandgap, reference current generators, regulators etc.
- Should be hands-on in the design of high-speed Tx and Rx and should have good knowledge on various challenges in their designs.
- Experience in the design of equalization circuits like FFE, CTLE, DFE is highly encouraged.
- DDR protocol experience is welcome.
- Exposure to package and PCB effects on DDR system performance is needed.
- Strong debugging skills during circuit simulations.
- Understanding of .lib and IBIS with respect to high-speed I/Os.
- Ability to co-work with team-members and should be a good team-player.
- Excellent communication and presentation skills.
- Need a good mindset to debug issues seen in silicon
|
Bengaluru, India |
