Responsibilities

• IP connectivity, IP configuration verification and Bus protocol verification at SoC level
• ASIC functional verification of IP multi-configuration and multi-protocol at SoC level
• Understand expected design functionalities, develop corresponding test plans, setup and develop components in verification environment
• Achieve coverage goals through various methodology, such as UVM, coverage-driven verification, transaction-level modeling, system verilog interface, virtual sequencer and etc.
• Manage projects and update weekly progress to customers

Requirements

• Familiar with Synopsys verification tools
• Excellent team and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in ARM CPU, PCIe or USB 3.x system verification is a plus
• At least 2 year working experience
• Candidate with 8 year experience or more will be considered for senior manger/technical lead position
• Candidate with less experience will be considered for junior position
  

Responsibilities

• Subsystem integration (PCIe, DDR, USB)
• Integrate controller and PHY at RTL level
• Integrate controller and PHY IP level SDC and generate subsystem level SDC
• Pass subsystem simulation
• Pass RTL QA items, such as CDC, Lint, and SDC validation
• Perform Synthesis (RTL to Netlist)
• Pass QA items, such as LEC, STA and in-house design kit
• Generate HDM model (subsystem CDC model, for SoC level CDC)
• Generate subsystem document & database package

Requirements

• Familiar with system verilog
• Familiar with front-end EDA tools
• Logic simulation tool, Cadence Xcelium or Synopsys VCS
• Synopsys design compiler, PrimeTime, Lint
• LEC tool, Cadence Conformal or Synopsys Formality
• Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
• Familiar with PCIe Gen-4 spec
• Familiar with AMBA AXI, AHB, APB spec
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in UVM is a plus
• At least 2 year working experience
• Candidate with 8 year experience or more will be considered for technical lead position
• Candidate with less experience will be considered for junior position

Responsibilities

• IP test-chip integration design and verification (memory IP and standard library IP)
• IP test chip development in advanced nodes
• Coordinate cross-site & cross-division communication & discussion
  

Requirements

• At least 2 year experience in RTL design and verification
• Familiar with digital design flow & tools: Verilog, VCS, Verdi, Xcelium, UPF…
• Scripting skills: Bash/C-shell, Perl, TCL, Python…
• Familiar with Synopsys design compiler flow
• Familiar with Primetime STA flow
• Basic knowledge on Cadence Innovus and layout EDA tools is a plus
• Basic knowledge on physical verification (DRC/LVS) is a plus
• Chip tape-out experience is a plus

Responsibilities

• SoC Integration (IP connectivity, IP configuration, Bus protocol design and etc.)
• Subsystem Integration (PCIe, DDR, USB and etc.)
• Integrate controller and PHY at RTL level
• Integrate controller and PHY IP level SDC, and generate subsystem level SDC
• Pass SoC, subsystem simulation
• Pass RTL QA items, such as CDC, Lint, and SDC validation
• Perform synthesis (RTL to Netlist)
• Pass QA items, such as LEC, STA, and in-house design kit
• Generate HDM model (subsystem CDC model, for SoC level CDC)
• Generate subsystem document & database package
• Manage projects and update weekly progress to customers

Requirements

• Familiar with System Verilog
• Familiar with Front-end EDA tools
• Logic simulation tool, Cadence Xcelium or Synopsys VCS
• Synopsys Design Compiler, PrimeTime, Lint
• LEC tool, Cadence Conformal or Synopsys Formality
• Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
• Familiar with PCIe Gen-4 spec.
• Familiar with AMBA AXI, AHB, APB spec.
• Experience in ARM CPU, PCIe or USB 3.x system verification is a plus
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in UVM is a plus
• At least 12 year working experience
• Candidate with 8 year experience or more will be considered for technical lead position
• Candidate with less experience will be considered for junior position

Responsibilities

• Static timing analysis and timing closure (TOP and block)
• Synthesis, low power check, logic equivalence check, clock tree guideline
• Collaborate with DFT teams to create and validate DFT circuit and SDC
• Discuss with customers for data-in qualification & sign-off condition
• Work as project leader/block coordinator to control project schedule and support project members to ensure T/O on-time

Requirements

• Familiar with PrimeTime, Debussy, Verilog-XL, design compiler and formal verification tools
• Excellent team-work and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• At least 2 year working experience

Responsibilities

• Define DFT specification, finalize DFT strategy to achieve the testing target
• Perform implementation and verification DFT circuit ( MBIST/SCAN/BSCAN/IP-Test)
• Define DFT SDC (timing constraint) strategy, collaborate with Backend engineer to validate DFT circuit & SDC
• Tester pattern generation and silicon debug analysis/diagnosis
• Work as project leader/block coordinator to control project schedule and support project members to ensure T/O on-time

Requirements

• Familiar with Tessent/TMAX, synthesis/simulation/formal verification tools
• Excellent team and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• At least 2 year working experience

Responsibilities

• ASIC physical implementation with automatic place and route tools
• Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization
• Physical verification signoff including DRC, LVS, ERC, Antenna and ESD
• Coordinate cross-site communication and coordination among internal supporting groups

Requirements

• Familiar with Cadence Innovus or Synopsys Fusion compiler flow
• Familiar with timing closure, IR drop analysis and physical verification
• Excellent team and interpersonal skills
• BS or MS degree in EE or CS related
• Good English communication skills
• At least 2 year working experience
• Candidate with 8 years experience or more will be considered for senior manger/technical lead position
• Candidate with less experience will be considered for junior position

Responsibilities

• Participate in ASIC development project with emphasis in place and route implementation (block, subsystem and/or top-level), timing closure, low power, physical verification, power analysis and IR/EM with package
• Coordinate and drive physical design activities of the SoC and support cross-functional engineering effort for signoff closure for tapeout
• Work closely with frontend, integrating as well as DFT team to optimize performance, power and area
• Participate in cutting-edge physical design methodology and flow development

Requirements

• Must be a power user of Cadence suite (Innovus, QRC, Voltus) or Synopsys suite (ICC2, Fusion Compiler, StarRC, PTSI)
• Strong in ASIC physical design flow with low power, performance and area optimization techniques
• Automation and programming-minded, solid coding experience in scripting languages
• Knowledge of logic design principles, and DFT concepts
• Successful track records of taping out SoCs in FinFet process is plus
• BS or MS degree in EE or CS related
• Good English communication skills
• At least 5 year working experience

Responsibilities

• Design, optimization and verification of IP memory compiler
• Design including high-speed, high-density or low-power variant
• Actively participate in design methodology and QA system improvement
• Cooperate with layout and CAD engineers for optimal schedule
• Assist testchip team in silicon verification and provide silicon validation report
• Provide mentorship and guidance to junior engineers

Requirements

• Solid knowledge on SRAM architecture and design methodology
• Solid knowledge on device physics, process variation and SRAM bit cell behavior
• Familiar with performance, power and area (PPA) design optimization
• Familiar with timing/power characterization, function verification and other SRAM compiler QA tool setup
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in FinFET is a plus
• At least 2 year working experience
• Candidate with 8 year experience or more will be considered for senior manger/technical lead position
• Candidate with less experience will be considered for junior position

Responsibilities

• Responsible for memory design automation utilities implementation
• Support and maintain existing in-house tools
• Responsible for memory characterization by using automatic characterization tools; characterization flow includes instance characterization and liberty generation
• Responsible for co-working with circuit designers to verify characterization results and trouble shooting
• Support cross-site communication between Taiwan CAD team and Vietnam design team

Requirements

• Familiar with any programming language, such as C/C++, TCL, or Python
• Familiar with EDA tools, such as circuit simulator, LPE tools, layout editor or schematic editor
• BS or MS degree in EE or CS related
• Good English communication skills
• Positive attitude and good team-work skills
• At least 2 years working experience
• Candidate with 8 years experience or more will be considered for senior manger/technical lead position
• Candidate with less experience will be considered for junior position

Responsibilities

• Responsible for standard cell library development in new process nodes
• Support customization through PPA optimization on architecture, circuit and design methodology
• Collaborate with multiple foundries and design methodology/flow team

Requirements

• Solid knowledge in standard cell library design and layout
• Solid knowledge in device physics and process variation
• BS or MS degree in EE or CS related
• Good English communication skills
• Experience in C-shell, TCL, C/C++, Perl or Python is a plus
• At least 2 years working experience
• Candidate with less experience will be considered for junior position

Responsibilities

• Study and perform physical verification deck QA
• Co-operate with circuit/layout team to define layout and QA methodologies for enhancing effectiveness and design quality
• Perform physical verification (LVS/DRC/ERC/EMIR)
• Ensure the database fully compliant with all requirements of tape-out flow
• Work with other engineers to achieve full chip integration, physical implementation, tape out and test-chip validation
• Work with IC design engineers to implement top quality layout for optimized block level design

Requirements

• At least 3 year experience in layout memory IP design
• Self-motivate, efficient professional to work independently or in team
• Experience in memory layout, such as SRAM/ROM/TCAM
• Experience in the memory layout structure, sense amplifier, low power design, and power management
• Experience in floor-planning techniques, power mesh palling, signal routing, and matching layout
• Experience in FinFET layout techniques is a plus
• Able to estimate the schedule for the assignment layout
• Proficient in Cadence/Synopsys layout editor and physical verification tools
• Good English communication skills

Responsibilities

• Responsible for layout floor-planning, hierarchical layout assembly, custom cell design, optimizing, and ect.
• Create, verify, and modify custom CMOS integrated circuit layouts, as directed by design engineers
• Plan place and route architecture
• Perform physical verification: DRC, LVS and Antenna
• Prepare presentation documents for customers

Requirements

• Bachelor/engineer or above in electrical engineering or relative major
• Good English communication skills
• Good communication skills, positive attitude, and team-work skills
• Self-learning ability