Advanced packaging technology enhances cost efficiency, improves performance, and overcomes reticle size limitation. It enables the integration of multiple dies, each fabricated using different process nodes for distinct functions. This architectural flexibility is no longer constrained by mask reticle size, allowing for scalable CPU arrays. More efficient I/O chiplets improve yield control, while the addition of GPUs, DPUs, or memory extensions reduces latency for enhanced performance. Furthermore, 3D packaging technology supports compact form factors, catering to wearable devices and other space-constrained applications.
Why Faraday
Faraday provides comprehensive packaging services, from traditional 2D towards advanced 2.5D/3D packaging, in collaboration with leading packaging suppliers. Our expertise in IP, design and logistics, together with a neutral, flexible business model, create a synergistic approach for successful advanced packaging solutions.
Through strategic partnerships, Faraday provides key elements in advanced packaging, including:
- Passive and Active Interposer with TSV
The TSV (Through-Silicon Via) process enables vertical electrical interconnects in passive interposer or logic dies, improving communication efficiency and reducing power consumption. - Memory(HBM, 3D Memory)
Heterogeneous memory integration provides high bandwidth and low-latency memory resources to enhance computing performance. Faraday collaborates with ecosystem partners to offer diverse memory solutions tailored to different packaging architectures. - Bumps
Advanced packaging technology supports higher electrical interconnect density through finer bump pitch and smaller bump sizes than traditional methods. Faraday works with packaging partners to provide comprehensive 2.5D/3D packaging solutions, containing micro-bump and hybrid bonding technologies.
2.5D Package Design Service
Faraday has led to offer a 2.5D consolidated platform integrating four key elements of Chiplet, HBM, interposer and substrate, and which are linked through design, packaging and production services to ensure successful delivery.
The features of the platform
- Flexible business model
- Highly customized: Faraday manages all elements, including chiplet design, HBM procurement, interposer design, packaging, and substrate design and manufacturing.
- Fast delivery: the platform supports chiplets from multi-foundries, significantly shortening time-to-market.
- Strong supply chain partnership
- Interposer: UMC and other leading suppliers
- Secure HBM memory supply
- Packaging: OSAT, Intel EMIB, Samsung 2.5D I-Cube
3D Packaging Design Service
3D packaging integrates multi-functional chiplets, such as SoCs, memory and accelerators, onto an active base die, delivering a compact form factor with enhanced power efficiency. The stacking can be achieved by micro-bump or hybrid bonding according to chiplet design requirements.
Faraday collaborates with Winbond, UMC and ASE to provide the customized high-bandwidth memory HiSpeedKit™-Cube platform, which is designed for edge AI, AR/VR video processing, wearable devices and other low-power, low-latency and high-memory bandwidth applications. Our expertise extends to developing memory controllers and I/O IP for Winbond’s ultra-bandwidth elements (CUBE), realizing HBM-like memory structure through wafer-to-wafer bonding and final packaging in UMC and ASE.
