Advanced package technology offers an upgraded choice for optimal cost, performance and size. Chips can be composed of several dies in different process nodes with different functions. The architecture design is no longer limited by mask reticle size, like scalable CPU array. I/O chiplets can be designed in optimized process nodes for better yield control. Performance can be enhanced with lower latency by added GPU/DPU or memory extension. Furthermore, 3D package technology brings small form factors to meet the requirement of wearable devices.


Why Faraday

As a neutral ASIC provider, Faraday offers one-stop shopping and business model for 2.5D/3D advanced package service. With robust design flow and experience, we can help integrate multi-vendor/source dies or so-called chiplets, and support customized interposer design and implementation and testing. In aspect of manufacturing, Faraday has kept long-term relationship with tier-1 vendors to secure capacity and quality for customers to achieve project success.

  • Interposer is the key for 2.5D/3D advanced package
    • Cooperating with UMC, Faraday provides design service for both passive and active interposers to guarantee the signal integrity
    • Faraday takes care of the simulation of power integrity and thermal analysis, and etc. in package design
  • Local Tier-1 suppliers of advanced package with long-term relationships
    • Excellent high-speed IP test experience
    • Robust 3D test flow to screen out interface defect to ensure reliability
    • Shorten developing schedule with on-site support at Taiwan OSAT
    • Fab-OSAT (KYEC, SPIL) turnkey model to ensure yield quality and lessen manufacture time
      * UMC has shipped more than 100k pieces of wafers for interposers since 2016


2.5D Package Design Service

In 2.5D package design, top dies with different functions, such as SoC dies, compute dies, memory dies, I/O dies, analog dies, are placed side by side through micro bumps (uBump) on a Silicon interposer. TSVs (Through Silicon Via) provide the connectivity to the substrate.

2.5D package technology is applied for achieving highest performance, targeting at HPC (High Performance Computing) like AI accelerator, graph processing unit, and networking processor.

3D Package Design Service

3D package integrates chiplets with multi-functions, such as SoC, memory and accelerator, on the 3D base die. It brings exceptional performance with small form factor and power saving.

3D package technology is applied for optimal performance, power and area, targeting at the applications that require small form factor, like Cloud, network and edge computing.