Architecture exploration and performance verification is essential to the development in early stage for designing complex SoCs. To help customers developing a competitive SoC product, Faraday co-works with customers from bus architecture design to application flow fine-tune, providing components and methodologies required to solve performance related issues in both hardware and software.

Under Faraday's SoC design service, performance exploration platform and virtual platform are both available to fulfill entire architecture design requirements. In addition to utilizing various efficient platforms, adoption of network-on-chip (NoC) technology also helps to make another leap forward in capabilities and flexibilities in tackling complex and large-scale SoC designs.

Performance Exploration Platform

An exploration platform can be built in the early phase of project to explore and validate the performance of the chip architecture. Essential components, such as traffic generator and performance monitor, will also be created accordingly. This architecture exploration methodology has been applied to plenty of successful projects. 

Virtual Platform

Faraday introduces Transaction-level modeling (TLM) technology to IP modeling to build up virtual platform efficiently; it is becoming standard practice to accelerate software availability in the industry. Moreover, workflows for performance simulation can be also derived from such facility.

Network on Chip 

Network-on-Chip (NoC) is an emerging paradigm for communications within SoC in place of traditional bus. It provides the flexibility to span the connection between wide-spread IPs in a large-scale IC and the capability to ease routing congestion issue. This technology has been successfully adopted on several large-scale SoC projects in Faraday. Appropriate flow and methodology have also been built up to tackle the front-end and back-end iterations for timing closure.