Faraday's FPGA-to-ASIC conversion service is introduced to meet the requirements of lower BOM cost, lower power consumption, higher integration for miniaturization, and long-term supply commitments, as well as a strategic response to FPGA End-of-Life (EOL) events. The service can customize an FPGA design or multiple chips/ components into a single ASIC or SoC, while maintaining the original design fidelity. Faraday has successfully implemented many FPGA conversion projects including the applications of industrial motor control, AI, water meters, digital billboards, POS terminals, and portable medical devices.



The benefits from FPGA-to-ASIC conversion

  • Feature improvement
  • Performance enhancement
  • Multiple FPGAs to single ASIC
  • Private design security
  • Power consumption reduction
  • Product improvement
  • Footprint size
  • BOM cost with much lower cost apiece
  • Production stability
  • Long product life cycle without the risk of FPGA EOL issue

Faraday’s design enablement

  • Over 3000 self-developed IP and IP subsystems to support IP replacement or customization within the FPGA-to-ASIC conversion process
  • MPS engine (Micro-Program Sequencing) for quick circuit function implementation
  • Completed ASIC/SoC design flow and methodology
  • SoCreative!™ platformof HPC and IoT for software and hardware co-development and system evaluation in early stage

Task FPGA Pure ASIC FPGA to ASIC
RTL design and verification v - v
IP connection & design integration v - v
IP selection/ configuration/ customization - - v
Design migration - - v
SoC verification v - v
Design rule checking - v v
Clock scheme and timing constraints Poor v v
Power management strategy design - v
v
FPGA prototype routing/verification v Optional v
Substrate & package v v v
Synthesis & routing - v v
ASIC implementation - v v
Chip testing - v v