FPGA-Go-ASIC™ prototyping platform is design for customers’ quick software and system verification. It is integrated abundant silicon-proven IP, such as ARM CPU Sub-system, PCIe, LVDS, DDR PHY and MIPI D-PHY. System designers can port their designs or connect the platform with their original designs via PCIe interface for whole system verification easily. To shorten time-to-market, customers may either apply the platforms to verify their designs or simply leave verification to Faraday.
Advantages of FPGA-Go-ASIC Prototyping Platform
- A real silicon CPU hardcore and high performance
Instead of an external CPU or a softcore, FPGA-Go-ASIC Prototyping Platform provides a real hardened ARM Cortax-A core and a real ARM bus architecture environment to verify SoC architecture. The CPU and ARM Bus help designers speed verification schedule and get accurate SoC performance. - Rich silicon-proven IP
Faraday FPGA-Go-ASIC Prototyping Platform integrates those silicon-proven IP that are frequently used in FPGA devices, such as 16G SerDes, PCIe PHY, DDR3/4, LPDDR3/4, and LVDS. It can reduce risk of porting mixed-signal IP in FPGA-to-ASIC design projects. - Complete ported software design Kit
FPGA-Go-ASIC Prototyping Platform supports complete software design kit and is ported a Linux OS with drivers. System designers can run their software in the development environment before their SoC/ASIC is completed. Hardware and software co-design is feasible.
Complete ported Software Design Kit
Faraday provides software design kit
- Open source Linux, FreeRTOS and CMSIS
- IP models, IP subsystems, IP drivers and testing programs
- IP middle wares including file system, TCP/IP protocol, USB protocol, PCIe protocols
- Multi-interface boot mode demos
- Security subsystem supports specific customized functions, such as RoT and secure boot
SoCreative!VI™ A600 SoC Development Platform
IP |
A600 | Zynq UltraScale+ MPSoC |
Zynq UltraScale+ RFSoC |
|
|---|---|---|---|---|
| CPU Subsystem | ARM Cortex-A53 Quad-core | Quad-core 1.5GHz | CG: Dual-core 1.3GHz EG, EV: Quad-core 1.5G |
Quad-core 1.3G |
| Cortex-R5F Dual-core | - | CG: 533MHz EG, EV: 600MHz |
Dual-core 533MHz | |
| CoreSight SoC 400 | ✓ | - | - | |
| SoC subsystem | Peripheral | DMA, GPIO, I2C, I2S UART, SPI |
DMA, GPIO, I2C, I2S UART, SPI, CAN |
DMA, UART, SPI, CAN |
| Memory I/F | xDDRn | LPDDR4X/4 | LPDDR4/3 DDR4/3/3L |
LPDDR4/3 DDR4/3/3L |
| EMMC/SD | ✓ | 2x SD/SDIO | 2x SD/SDIO | |
| HyperBus | For SRAM, Flash | - | - | |
| Accelerator/ engine | Graphic Engine | FPGA based | - | - |
| Display Engine | ✓ | - | - | |
| Video Engine | H.265 | EV: H.264/H.265 | - | |
| Mixed-signal IP | PCIe | PCIe Gen4 4-lane | PCIe Gen2 4-lane | Gen1/Gen2: PCIe Gen3 Gen3: PCIe Gen4, CCIX |
| USB | USB 2.0 OTG PHY | USB 3.0, USB 2.0 x2 | USB 3.0 | |
| Digital IP | USB 2.0 controller | ✓ | ✓ | - |
| GbE MAC | ✓ | 4x Tri-mode Gigabit Ethernet | ||
| Security | Root of Trust (Soteria) | RSA, AES, SHA | AES, secure boot | |
| Logic Element | Flexible | 81K~600K | 489K~930K | |
FIE3240 FPGA Platform
IP |
FIE3240 | |
|---|---|---|
| CPU subsystem | ARM CPU | M0/M3/M4 48MHz |
| RISC-V | FIE3240N25-F | |
| SoC subsystem |
Peripheral | DMA, UART, SPI, I2C, SSP |
| Memory I/F | EMMC/SD | SDIO/SDHC |
| Mixed-signal IP | PCIe | PCIe Gen2 x2 |
| USB | USB 3.0, USB 2.0 OTG | |
| ADC | 10-bit, 8-channel | |
| Digital IP | GbE MAC | 10/100M MAC |
| TFT-LCD controller | ✓ | |
| LCM controller | 8-bit/16-bit/18-bit | |
| Security | AES, secure boot | |
| Logic Element | 326K | |