To guarantee the quality of integration delivery and to increase the confidence level of tape-out, various techniques are involved to achieve full verification closure. As complexity of chip design grows, coverage metrics become critical to measuring and guiding the verification process. Integrated tools and rigid verification methodologies are thus adopted to boost the process toward full coverage. These require a wide range of domain know-how and advanced methodologies to execute accurately and efficiently. In Faraday, such infrastructure and business model have been built up and applied to projects in diversified applications successfully.


SystemVerilog Assertion (SVA)

SystemVerilog assertions are used to validate the behavior of a design and provide functional coverage information for a design. It reveals an efficient and accurate way to ensure the SoC integration quality. The technology is used extensively among various domains, such as clock, reset, protocol, and power, to detect design flaws as early as possible in the design stage.



Universal Verification Methodology (UVM)

Universal verification methodology is a methodology and a library that codifies the best practices for efficient and exhaustive verification. It provides a framework to achieve coverage-driven verification (CDV) for

  • Reduce the effort and time into hundreds of tests
  • Ensure up-front goal setting used in thorough verification

In addition, IP-XACT is used to enable automation for UVM register packages, allowing efficient HW/SW interface verification through UVM. Since the IP control and coverage are completed at the register level, UVM register package enables verification process done much more efficiently and thoroughly.

Faraday builds up the verification environment based on UVM test bench architecture as below. Connecting to various VIP models, the test bench can verify system-level functionality, especially for complex SoC. With those mentioned above, it provides a solid, reliable verification environment.



Low Power

The imperative for reducing power consumption results in the use of a multiplicity of power reduction methods, such as power domains and clock gating techniques. To achieve the requisite low power characteristics and minimize or even completely avoid late-stage redesign, the appropriate reduction techniques have to be verified at RTL, which includes:

  • Exhaustive functional verification at RTL level, both before and after the deployment of power optimization circuitry
  • Verification of hardware functionality compliance with software control sequences



Clock Domain Crossing

A majority of today's designs contain multiple clocks, and all such designs can potentially fail if communication between clock domains is not correctly synchronized. The detection and elimination of potential problem in multi-clock design thus is one of the key components in Faraday's complete verification flow.


Verification IP

SystemVerilog and UVM provide a consistent language and methodology, which is important when verification IP (VIP) and test bench are exchanged among different teams/parties. In Faraday, UVM VIPs are used across IP-level verification and system-level verification during the whole development process. And, in order to satisfy various SoC verification requirements, we commit to have a wide range of VIP category in the repository.