The Faraday 28Gbps multi-protocol programmable SerDes PHY IP at UMC 28nm node is designed with a system-level approach to provide outstanding metrics across power, performance and area. This SerDes PHY can readily support the optimization of SoC chip designs to enable the infrastructure of 100G Ethernet, PCIe 4.0, 5G, and most xPON applications.

This full-duplex and high-performance SerDes solution comes with a scalable PMA, supporting data rates up to 28Gbps across copper and backplane channels with more than 32dB of total insertion loss in a wide range of interconnect protocols. This state-of-the-art design is compatible with standard PCS and controller to address enterprise-class performance for data communication and networking systems.

28G SerDes PHY Demonstration Video

 

Highlights

  • Supports OIF-CEI-28G VSR/SR and OIF-CEI-25G LR
  • Supports PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
  • Supports 25Gb to 100Gb Ethernet: 25G/50G/100G-KR4&CR4
  • Supports JESD204B/C for high-speed ADC/DAC and FPGA interface
  • Supports xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym 10GEPON
  • PVT compensated PMA hard macro optimized for multi-protocols
  • Multi-Interface enables 3rd party’s PCS/MAC’s direct connection to PMA
  • Soft PCS IP is available for PCIe 4.0 applications
  • PMA data width for 16/20/32/40 bits
  • Full-duplex lane configuration of x1, x2, x4
  • Ultra-low-power 4 TAP FIR voltage-mode driver with programmable swing and amplitude
  • Receiver with built-in AC coupling cap, adaptive CTLE/VGA equalizer, and 14 TAP DFE
  • Multiple internal /external loopbacks (TX to RX, RX to TX, RX loopback after S2P with RX clock)
  • On-chip eye scan monitor for testing
  • Built-in power-saving states
  • Built-in PRBS & programmable pattern generator and checker
  • FOM for link training
  • Extensive auto-calibration and BIST engine for performance tuning and self-diagnostics
  • Support up to 600 ppm offset and up to 5000ppm SSC