The 40ULP IPs include Faraday PowerSlash™ IPs, which are the fundamental building blocks for a low-power design, including multi-Vt libraries and a comprehensive power management kit.
Standard Cell (Readiness)
| Item | LVT C40 | RVT C40 | HVT C40 | LVT C50 | RVT C50 | HVT C50 | Note | |
|---|---|---|---|---|---|---|---|---|
| 7T | Base library | - | ||||||
| Power slash kit | - | - | - | - | ||||
| ECO library | - | - | - | - | ||||
| 9T | Base library | - | ||||||
| Power slash kit | - | - | - | - | ||||
| ECO library | - | - | - | - | ||||
| TGO (RTC) | Base library | - | - | - | - | - | I/O device | |
Features
- 7/9 track high cell for high density and low power requirement
- DC power saving up to 87% from RVT to HVT
- DC power saving up to 15% from C40 to C50 for HVT
- Same footprint cell layout for cell fusion for synthesis and P&R
- Operation voltage: 1.21V - 0.99V; Vcc_min= 0.99v
- 16T TGO cell library for RTC and always-on circuit
Memory Compiler & I/O IP
| Item | Feature | Readiness |
|---|---|---|
| Memory Compiler | RVT SPRAM | |
| RVT 1PRF | ||
| RVT 2PRF | ||
| RVT DPSRAM | ||
| RVT TCAM | ||
| RVT VIA ROM | ||
| LVT SPRAM | ||
| LVT 1PRF | ||
| LVT DPSRAM | ||
| LVT VIA ROM | ||
| HVT SPRAM | ||
| HVT 1PRF | ||
| RVT power gating SPRAM | ||
| RVT power gating 1PRF | ||
| RVT power gating 2PRF | ||
| RVT power gating DPSRAM | ||
| RVT power gating VIA ROM | ||
| LVT power gating 1PRF | ||
| LVT power gating 2PRF | ||
| LVT power gating DPSRAM | ||
| LVT power gating VIA ROM | ||
| HVT power gating SPRAM |
